1. Field of the Invention:
The present invention relates to a semiconductor device and a method for producing the same, in particular, to a bipolar LSI and a BiMOS LSI and a method for producing the same.
2. Description of the Prior Art:
FIGS. 3a through 3d sequentially illustrate a common method for producing a bipolar LSI. The method will be described with reference to the figures.
AS is shown in FIG. 3a, an n.sup.+ buried layer 11 is formed in a specified pattern at a surface of a p-silicon substrate 10, and then an n.sup.- epitaxial layer 12 is formed by epitaxial growth.
Next, as is shown in FIG. 3b, a p.sup.+ isolating layer 14 is formed by diffusing a p.sup.+ ion in the n.sup.- epitaxial layer 12 for isolation. A silicon oxide film 13 is formed at a surface of the n.sup.- epitaxial layer 12 by selective oxidation. Then, an n.sup.+ collector region 15 is formed by diffusion of an n.sup.+ ion.
As is shown in FIG. 3c, a p-base region 16 is formed at an area of a surface of the n.sup.- epitaxial layer 12, the area having no silicon oxide film 13, and then an n.sup.+ emitter region 17 is formed within the p-base region 16.
As is shown in FIG. 3d, a window is formed in each of the n.sup.+ collector region 15, the p-base region 16, and the n.sup.+ emitter region 17, and then a collector electrode C, a base electrode B, and an emitter electrode E are formed at the respective windows in specified patterns by depositing aluminum by use of a sputtering method.
In a bipolar LSI produced in the abovementioned conventional method, a parasitic pnp transistor 18 is formed by the p-base region 16, the n.sup.- epitaxial layer 12, the p.sup.+ isolating layer 14 and the p-silicon substrate 10 as is shown in FIG. 4. The parasitic pnp transistor 18 causes problems such as latch-up during the operation of the bipolar LSI, which results in a malfunction.